1. Field of the Invention
The present invention relates to the field of stacked semiconductor devices, and more specifically to generating a unique device identifier for addressing each stacked device.
2. Discussion of Related Art
Addressable devices typically require some way by which each device can be addressed independently from other devices residing on the same bus. Addressable devices used in conventionally bonded stacked configurations may provide this capability by assigning each device a unique device identifier (ID). The device ID may be configured in the assembly process by bonding several device ID bondpads to power (Vcc) or ground (Vss), thereby encoding a unique device ID.
FIG. 1 illustrates an exemplary approach of the current art for generating a device ID for a stacked memory device. FIG. 1 illustrates a cross-section of a package 100. The package 100 contains a package substrate 102 and two stacked memory devices 104 and 106 stacked on top of the package substrate. Memory devices 104 and 106 are bonded to substrate 102 by bond wires 116. The bond wires electrically connect the bondpads of each device to the package substrate 102. Device ID signal bond pads 107 and 108 are each connected to ground (Vss) in the package substrate. This generates a device ID of 00 for memory device 104. Device ID signal bond pad 109 is connected to ground (Vss) in the package substrate. Device ID signal bond pad 110 is connected to power (Vcc) in the package substrate. This generates a device ID of 01 for memory device 106. When two signals on each addressable device are used to generate a device ID using this conventional method, four unique device IDs can be generated, supporting four addressable devices on a bus.
Alternatively, the device ID of a device is encoded in the printed circuit board substrate, rather than in the package substrate, as shown in FIG. 2. FIG. 2 illustrates a cross-section of a package 100 on a printed circuit board 120. Package 100 contains a package substrate 102 and two stacked memory devices 104 and 106. Memory devices 104 and 106 are bonded to substrate 102 by bond wires 116. The bond wires electrically connect the bondpads of each device to the package substrate 102. Each device ID signal is routed from the bond wire 116 through the package substrate 102 as a conductive trace 118. The package 100 is connected to the printed circuit board through interconnects 124. Device ID signal bond pads 107 and 108 are each connected to ground (Vss) in the printed circuit board through the bond wires 116, conductive traces 118, and interconnects 124. This generates a device ID of 00 for memory device 104. Device ID signal bond pad 109 is connected to ground (Vss) in the printed circuit board through the bond wires 116, conductive traces 118, and electrical connections 124. Device ID signal bond pad 110 is connected to power (Vcc) in the printed circuit board through the bond wires 116, conductive traces 118, and electrical connections 124. This generates a device ID of 01 for memory device 106.
Future memory devices may utilize new technologies in packaging stacked devices, such as through-silicon vias or optical technology. The conventional method of bonding out a unique device ID for each stacked device, as described above, may not be practical for future device stacking technologies.